/** @file
 *
 *  Copyright (c) 2021, Jared McNeill <jmcneill@invisible.ca>
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
 **/

#ifndef RK356XVOP2_H__
#define RK356XVOP2_H__

#define VOP2_SYSREG_BASE                    (VOP_BASE + 0x0000)
#define VOP2_OVERLAY_BASE                   (VOP_BASE + 0x0600)
#define VOP2_POSTn_BASE(n)                  (VOP_BASE + 0x0C00 + (0x100 * (n)))
#define VOP2_CLUSTERn_BASE(n)               (VOP_BASE + 0x1000 + (0x200 * (n)))
#define VOP2_ESMARTn_BASE(n)                (VOP_BASE + 0x1800 + (0x200 * (n)))

/* System registers */

#define VOP2_SYS_REG_CFG_DONE               (VOP2_SYSREG_BASE + 0x0000)
#define  VOP2_SYS_REG_CFG_DONE_SW_GLOBAL_REGDONE_EN BIT15
#define  VOP2_SYS_REG_CFG_DONE_REG_LOAD_ESMART0_EN  BIT10
#define  VOP2_SYS_REG_CFG_DONE_REG_LOAD_GLOBAL0_EN  BIT0
#define VOP2_SYS_VERSION_INFO               (VOP2_SYSREG_BASE + 0x0004)
#define VOP2_SYS_AUTO_GATING_CTRL_IMD       (VOP2_SYSREG_BASE + 0x0008)
#define VOP2_SYS_AXI_CTRL0_IMD              (VOP2_SYSREG_BASE + 0x0010)
#define VOP2_SYS_AXI_HURRY_CTRL0_IMD        (VOP2_SYSREG_BASE + 0x0014)
#define VOP2_SYS_AXI_HURRY_CTRL1_IMD        (VOP2_SYSREG_BASE + 0x0018)
#define VOP2_SYS_AXI_OUTSTANDING_CTRL0_IMD  (VOP2_SYSREG_BASE + 0x001C)
#define VOP2_SYS_AXI_OUTSTANDING_CTRL1_IMD  (VOP2_SYSREG_BASE + 0x0020)
#define VOP2_SYS_AXI_LUT_CTRL_IMD           (VOP2_SYSREG_BASE + 0x0024)
#define VOP2_SYS_DSP_INFACE_EN              (VOP2_SYSREG_BASE + 0x0028)
#define  VOP2_SYS_DSP_INFACE_EN_HDMI_OUT_EN         BIT1
#define VOP2_SYS_DSP_INFACE_CTRL            (VOP2_SYSREG_BASE + 0x002C)
#define VOP2_SYS_DSP_INFACE_POL             (VOP2_SYSREG_BASE + 0x0030)
#define  VOP2_SYS_DSP_INFACE_POL_REGDONE_IMD_EN     BIT28
#define  VOP2_SYS_DSP_INFACE_POL_HDMI_DCLK_POL      BIT7
#define  VOP2_SYS_DSP_INFACE_POL_HDMI_DEN_POL       BIT6
#define  VOP2_SYS_DSP_INFACE_POL_HDMI_VSYNC_POL     BIT5
#define  VOP2_SYS_DSP_INFACE_POL_HDMI_HSYNC_POL     BIT4
#define VOP2_SYS_WB_CTRL0                   (VOP2_SYSREG_BASE + 0x0040)
#define VOP2_SYS_WB_XSPD_FACTOR             (VOP2_SYSREG_BASE + 0x0044)
#define VOP2_SYS_WB_YRGB_MST                (VOP2_SYSREG_BASE + 0x0048)
#define VOP2_SYS_WB_CBR_MST                 (VOP2_SYSREG_BASE + 0x004C)
#define VOP2_SYS_OTP_WIN_EN_IMD             (VOP2_SYSREG_BASE + 0x0050)
#define  VOP2_SYS_OTP_WIN_EN_IMD_OTP_EN             BIT0
#define VOP2_SYS_LUT_PORT_SEL               (VOP2_SYSREG_BASE + 0x0058)
#define VOP2_SYS_STATUS0                    (VOP2_SYSREG_BASE + 0x0060)
#define VOP2_SYS_STATUS1                    (VOP2_SYSREG_BASE + 0x0064)
#define VOP2_SYS_STATUS2                    (VOP2_SYSREG_BASE + 0x0068)
#define VOP2_SYS_LINE_FLAG0                 (VOP2_SYSREG_BASE + 0x0070)
#define VOP2_SYS_LINE_FLAG1                 (VOP2_SYSREG_BASE + 0x0074)
#define VOP2_SYS_LINE_FLAG2                 (VOP2_SYSREG_BASE + 0x0078)
#define VOP2_SYS0_INTR_EN                   (VOP2_SYSREG_BASE + 0x0080)
#define VOP2_SYS0_INTR_CLR                  (VOP2_SYSREG_BASE + 0x0084)
#define VOP2_SYS0_INTR_STATUS               (VOP2_SYSREG_BASE + 0x0088)
#define VOP2_SYS0_INTR_RAW_STATUS           (VOP2_SYSREG_BASE + 0x008C)
#define VOP2_SYS1_INTR_EN                   (VOP2_SYSREG_BASE + 0x0090)
#define VOP2_SYS1_INTR_CLR                  (VOP2_SYSREG_BASE + 0x0094)
#define VOP2_SYS1_INTR_STATUS               (VOP2_SYSREG_BASE + 0x0098)
#define VOP2_SYS1_INTR_RAW_STATUS           (VOP2_SYSREG_BASE + 0x009C)
#define VOP2_PORT0_INTR_EN                  (VOP2_SYSREG_BASE + 0x00A0)
#define VOP2_PORT0_INTR_CLR                 (VOP2_SYSREG_BASE + 0x00A4)
#define VOP2_PORT0_INTR_STATUS              (VOP2_SYSREG_BASE + 0x00A8)
#define VOP2_PORT0_INTR_RAW_STATUS          (VOP2_SYSREG_BASE + 0x00AC)
#define VOP2_PORT1_INTR_EN                  (VOP2_SYSREG_BASE + 0x00B0)
#define VOP2_PORT1_INTR_CLR                 (VOP2_SYSREG_BASE + 0x00B4)
#define VOP2_PORT1_INTR_STATUS              (VOP2_SYSREG_BASE + 0x00B8)
#define VOP2_PORT1_INTR_RAW_STATUS          (VOP2_SYSREG_BASE + 0x00BC)
#define VOP2_PORT2_INTR_EN                  (VOP2_SYSREG_BASE + 0x00C0)
#define VOP2_PORT2_INTR_CLR                 (VOP2_SYSREG_BASE + 0x00C4)
#define VOP2_PORT2_INTR_STATUS              (VOP2_SYSREG_BASE + 0x00C8)
#define VOP2_PORT2_INTR_RAW_STATUS          (VOP2_SYSREG_BASE + 0x00CC)
#define VOP2_AFBCD_INTR_EN                  (VOP2_SYSREG_BASE + 0x00E0)
#define VOP2_AFBCD_INTR_CLR                 (VOP2_SYSREG_BASE + 0x00E4)
#define VOP2_AFBCD_INTR_STATUS              (VOP2_SYSREG_BASE + 0x00E8)
#define VOP2_AFBCD_INTR_RAW_STATUS          (VOP2_SYSREG_BASE + 0x00EC)

/* Overlay registers */

#define VOP2_OVERLAY_CTRL                   (VOP2_OVERLAY_BASE + 0x0000)
#define  VOP2_OVERLAY_CTRL_LAYER_SEL_REGDONE_SEL_IMD    (BIT31|BIT30)
#define  VOP2_OVERLAY_CTRL_LAYER_SEL_REGDONE_IMD        BIT28
#define VOP2_LAYER_SEL                      (VOP2_OVERLAY_BASE + 0x0004)
#define VOP2_PORT_SEL                       (VOP2_OVERLAY_BASE + 0x0008)
#define VOP2_CLUSTERn_MIX_SRC_COLOR_CTRL(n) (VOP2_OVERLAY_BASE + 0x0010 + (0x10 * (n)))
#define VOP2_CLUSTERn_MIX_DST_COLOR_CTRL(n) (VOP2_OVERLAY_BASE + 0x0014 + (0x10 * (n)))
#define VOP2_CLUSTERn_MIX_SRC_ALPHA_CTRL(n) (VOP2_OVERLAY_BASE + 0x0018 + (0x10 * (n)))
#define VOP2_CLUSTERn_MIX_DST_ALPHA_CTRL(n) (VOP2_OVERLAY_BASE + 0x001C + (0x10 * (n)))
#define VOP2_MIXn_SRC_COLOR_CTRL(n)         (VOP2_OVERLAY_BASE + 0x0050 + (0x10 * (n)))
#define VOP2_MIXn_DST_COLOR_CTRL(n)         (VOP2_OVERLAY_BASE + 0x0054 + (0x10 * (n)))
#define VOP2_MIXn_SRC_ALPHA_CTRL(n)         (VOP2_OVERLAY_BASE + 0x0058 + (0x10 * (n)))
#define VOP2_MIXn_DST_ALPHA_CTRL(n)         (VOP2_OVERLAY_BASE + 0x005C + (0x10 * (n)))
#define VOP2_HDR0_SRC_COLOR_CTRL            (VOP2_OVERLAY_BASE + 0x00C0)
#define VOP2_HDR0_DST_COLOR_CTRL            (VOP2_OVERLAY_BASE + 0x00C4)
#define VOP2_HDR0_SRC_ALPHA_CTRL            (VOP2_OVERLAY_BASE + 0x00C8)
#define VOP2_HDR0_DST_ALPHA_CTRL            (VOP2_OVERLAY_BASE + 0x00CC)
#define VOP2_DPn_BG_MIX_CTRL(n)             (VOP2_OVERLAY_BASE + 0x00E0 + (0x4 * (n)))
#define  VOP2_DPn_BG_MIX_CTRL_DP_BG_DLY_NUM_SHIFT       24
#define  VOP2_DPn_BG_MIX_CTRL_DP_BG_DLY_NUM_MASK        (0xFFU << VOP2_DPn_BG_MIX_CTRL_DP_BG_DLY_NUM_SHIFT)
#define VOP2_CLUSTER_DLY_NUM                (VOP2_OVERLAY_BASE + 0x00F0)
#define VOP2_SMART_DLY_NUM                  (VOP2_OVERLAY_BASE + 0x00F8)

/* Post-process registers */

#define VOP2_POSTn_DSP_CTRL(n)              (VOP2_POSTn_BASE(n) + 0x0000)
#define  VOP2_POSTn_DSP_CTRL_VOP_STANDBY_EN_IMD     BIT31
#define  VOP2_POSTn_DSP_CTRL_DSP_OUT_MODE           (BIT3|BIT2|BIT1|BIT0)
#define  VOP2_POSTn_DSP_CTRL_DSP_OUT_MODE_24BIT     0
#define  VOP2_POSTn_DSP_CTRL_DSP_OUT_MODE_30BIT     15
#define VOP2_POSTn_MIPI_CTRL(n)             (VOP2_POSTn_BASE(n) + 0x0004)
#define VOP2_POSTn_COLOR_CTRL(n)            (VOP2_POSTn_BASE(n) + 0x0008)
#define VOP2_POSTn_3D_LUT_CTRL(n)           (VOP2_POSTn_BASE(n) + 0x0010)
#define VOP2_POSTn_3D_LUT_R(n)              (VOP2_POSTn_BASE(n) + 0x0014)
#define VOP2_POSTn_3D_LUT_G(n)              (VOP2_POSTn_BASE(n) + 0x0018)
#define VOP2_POSTn_3D_LUT_B(n)              (VOP2_POSTn_BASE(n) + 0x001C)
#define VOP2_POSTn_3DLUT_MST(n)             (VOP2_POSTn_BASE(n) + 0x0020)
#define VOP2_POSTn_DSP_BG(n)                (VOP2_POSTn_BASE(n) + 0x002C)
#define VOP2_POSTn_PRE_SCAN_HTIMING(n)      (VOP2_POSTn_BASE(n) + 0x0030)
#define VOP2_POSTn_DSP_HACT_INFO(n)         (VOP2_POSTn_BASE(n) + 0x0034)
#define VOP2_POSTn_DSP_VACT_INFO(n)         (VOP2_POSTn_BASE(n) + 0x0038)
#define VOP2_POSTn_SCL_FACTOR_YRGB(n)       (VOP2_POSTn_BASE(n) + 0x003C)
#define VOP2_POSTn_SCL_CTRL(n)              (VOP2_POSTn_BASE(n) + 0x0040)
#define VOP2_POSTn_DSP_VACT_INFO_F1(n)      (VOP2_POSTn_BASE(n) + 0x0044)
#define VOP2_POSTn_DSP_HTOTAL_HS_END(n)     (VOP2_POSTn_BASE(n) + 0x0048)
#define VOP2_POSTn_DSP_HACT_ST_END(n)       (VOP2_POSTn_BASE(n) + 0x004C)
#define VOP2_POSTn_DSP_VTOTAL_VS_END(n)     (VOP2_POSTn_BASE(n) + 0x0050)
#define VOP2_POSTn_DSP_VACT_ST_END(n)       (VOP2_POSTn_BASE(n) + 0x0054)
#define VOP2_POSTn_DSP_VS_ST_END_F1(n)      (VOP2_POSTn_BASE(n) + 0x0058)
#define VOP2_POSTn_DSP_VACT_ST_END_F1(n)    (VOP2_POSTn_BASE(n) + 0x005C)
#define VOP2_POSTn_BCSH_CTRL(n)             (VOP2_POSTn_BASE(n) + 0x0060)
#define VOP2_POSTn_BCSH_BCS(n)              (VOP2_POSTn_BASE(n) + 0x0064)
#define VOP2_POSTn_BCSH_H(n)                (VOP2_POSTn_BASE(n) + 0x0068)
#define VOP2_POSTn_BCSH_COLOR_BAR(n)        (VOP2_POSTn_BASE(n) + 0x006C)
#define VOP2_POSTn_FRC_LOWER01_0(n)         (VOP2_POSTn_BASE(n) + 0x00A0)
#define VOP2_POSTn_FRC_LOWER01_1(n)         (VOP2_POSTn_BASE(n) + 0x00A4)
#define VOP2_POSTn_FRC_LOWER10_0(n)         (VOP2_POSTn_BASE(n) + 0x00A8)
#define VOP2_POSTn_FRC_LOWER10_1(n)         (VOP2_POSTn_BASE(n) + 0x00AC)
#define VOP2_POSTn_FRC_LOWER11_0(n)         (VOP2_POSTn_BASE(n) + 0x00B0)
#define VOP2_POSTn_FRC_LOWER11_1(n)         (VOP2_POSTn_BASE(n) + 0x00B4)

/* Cluster registers */

#define VOP2_CLUSTER_WIN0_CTRL0(n)              (VOP2_CLUSTERn_BASE(n) + 0x0000)
#define VOP2_CLUSTER_WIN0_CTRL1(n)              (VOP2_CLUSTERn_BASE(n) + 0x0004)
#define VOP2_CLUSTER_WIN0_CTRL2(n)              (VOP2_CLUSTERn_BASE(n) + 0x0008)
#define VOP2_CLUSTER_WIN0_YRGB_MSG(n)           (VOP2_CLUSTERn_BASE(n) + 0x0010)
#define VOP2_CLUSTER_WIN0_VIR(n)                (VOP2_CLUSTERn_BASE(n) + 0x0018)
#define VOP2_CLUSTER_WIN0_ACT_INFO(n)           (VOP2_CLUSTERn_BASE(n) + 0x0020)
#define VOP2_CLUSTER_WIN0_DSP_INFO(n)           (VOP2_CLUSTERn_BASE(n) + 0x0024)
#define VOP2_CLUSTER_WIN0_DSP_ST(n)             (VOP2_CLUSTERn_BASE(n) + 0x0028)
#define VOP2_CLUSTER_WIN0_DSP_BG(n)             (VOP2_CLUSTERn_BASE(n) + 0x002C)
#define VOP2_CLUSTER_WIN0_SCL_FACTOR_YRGB(n)    (VOP2_CLUSTERn_BASE(n) + 0x0030)
#define VOP2_CLUSTER_WIN0_SCL_OFFSET(n)         (VOP2_CLUSTERn_BASE(n) + 0x0038)
#define VOP2_CLUSTER_WIN0_TRANSFORMED_OFFSET(n) (VOP2_CLUSTERn_BASE(n) + 0x003C)
#define VOP2_CLUSTER_WIN0_AFBCD_OUTPUT_CTRL(n)  (VOP2_CLUSTERn_BASE(n) + 0x0050)
#define VOP2_CLUSTER_WIN0_AFBCD_MODE(n)         (VOP2_CLUSTERn_BASE(n) + 0x0054)
#define VOP2_CLUSTER_WIN0_AFBCD_HDR_PTR(n)      (VOP2_CLUSTERn_BASE(n) + 0x0058)
#define VOP2_CLUSTER_WIN0_AFBCD_VIR_WIDTH(n)    (VOP2_CLUSTERn_BASE(n) + 0x005C)
#define VOP2_CLUSTER_WIN0_AFBCD_SIZE(n)         (VOP2_CLUSTERn_BASE(n) + 0x0060)
#define VOP2_CLUSTER_WIN0_AFBCD_PIC_OFFSET(n)   (VOP2_CLUSTERn_BASE(n) + 0x0064)
#define VOP2_CLUSTER_WIN0_AFBCD_DIS_OFFSET(n)   (VOP2_CLUSTERn_BASE(n) + 0x0068)
#define VOP2_CLUSTER_WIN0_AFBCD_CTRL(n)         (VOP2_CLUSTERn_BASE(n) + 0x006C)
#define VOP2_CLUSTER_WIN1_CTRL0(n)              (VOP2_CLUSTERn_BASE(n) + 0x0080)
#define VOP2_CLUSTER_WIN1_CTRL1(n)              (VOP2_CLUSTERn_BASE(n) + 0x0084)
#define VOP2_CLUSTER_WIN1_CTRL2(n)              (VOP2_CLUSTERn_BASE(n) + 0x0088)
#define VOP2_CLUSTER_WIN1_YRGB_MSG(n)           (VOP2_CLUSTERn_BASE(n) + 0x0090)
#define VOP2_CLUSTER_WIN1_VIR(n)                (VOP2_CLUSTERn_BASE(n) + 0x0098)
#define VOP2_CLUSTER_WIN1_ACT_INFO(n)           (VOP2_CLUSTERn_BASE(n) + 0x00A0)
#define VOP2_CLUSTER_WIN1_DSP_INFO(n)           (VOP2_CLUSTERn_BASE(n) + 0x00A4)
#define VOP2_CLUSTER_WIN1_DSP_ST(n)             (VOP2_CLUSTERn_BASE(n) + 0x00A8)
#define VOP2_CLUSTER_WIN1_DSP_BG(n)             (VOP2_CLUSTERn_BASE(n) + 0x00AC)
#define VOP2_CLUSTER_WIN1_SCL_FACTOR_YRGB(n)    (VOP2_CLUSTERn_BASE(n) + 0x00B0)
#define VOP2_CLUSTER_WIN1_SCL_OFFSET(n)         (VOP2_CLUSTERn_BASE(n) + 0x00B8)
#define VOP2_CLUSTER_WIN1_TRANSFORMED_OFFSET(n) (VOP2_CLUSTERn_BASE(n) + 0x00BC)
#define VOP2_CLUSTER_WIN1_AFBCD_OUTPUT_CTRL(n)  (VOP2_CLUSTERn_BASE(n) + 0x00D0)
#define VOP2_CLUSTER_WIN1_AFBCD_MODE(n)         (VOP2_CLUSTERn_BASE(n) + 0x00D4)
#define VOP2_CLUSTER_WIN1_AFBCD_HDR_PTR(n)      (VOP2_CLUSTERn_BASE(n) + 0x00D8)
#define VOP2_CLUSTER_WIN1_AFBCD_VIR_WIDTH(n)    (VOP2_CLUSTERn_BASE(n) + 0x00DC)
#define VOP2_CLUSTER_WIN1_AFBCD_SIZE(n)         (VOP2_CLUSTERn_BASE(n) + 0x00E0)
#define VOP2_CLUSTER_WIN1_AFBCD_PIC_OFFSET(n)   (VOP2_CLUSTERn_BASE(n) + 0x00E4)
#define VOP2_CLUSTER_WIN1_AFBCD_DIS_OFFSET(n)   (VOP2_CLUSTERn_BASE(n) + 0x00E8)
#define VOP2_CLUSTER_WIN1_AFBCD_CTRL(n)         (VOP2_CLUSTERn_BASE(n) + 0x00EC)
#define VOP2_CLUSTER_CTRL(n)                    (VOP2_CLUSTERn_BASE(n) + 0x0100)
#define VOP2_CLUSTER_LG_COE0(n)                 (VOP2_CLUSTERn_BASE(n) + 0x0110)
#define VOP2_CLUSTER_LG_COE1(n)                 (VOP2_CLUSTERn_BASE(n) + 0x0114)
#define VOP2_CLUSTER_LG_COE2(n)                 (VOP2_CLUSTERn_BASE(n) + 0x0118)
#define VOP2_CLUSTER_HG_COE0(n)                 (VOP2_CLUSTERn_BASE(n) + 0x0120)
#define VOP2_CLUSTER_HG_COE1(n)                 (VOP2_CLUSTERn_BASE(n) + 0x0124)
#define VOP2_CLUSTER_HG_COE2(n)                 (VOP2_CLUSTERn_BASE(n) + 0x0128)

/* Esmart registers */

#define VOP2_ESMART_CTRL0(n)                    (VOP2_ESMARTn_BASE(n) + 0x0000)
#define VOP2_ESMART_CTRL1(n)                    (VOP2_ESMARTn_BASE(n) + 0x0004)
#define VOP2_ESMART_REGION0_MST_CTL(n)          (VOP2_ESMARTn_BASE(n) + 0x0010)
#define  VOP2_ESMART_REGION0_MST_CTL_DATA_FMT_SHIFT     1
#define  VOP2_ESMART_REGION0_MST_CTL_DATA_FMT_MASK      (0x1FU << VOP2_ESMART_REGION0_MST_CTL_DATA_FMT_SHIFT)
#define  VOP2_ESMART_REGION0_MST_CTL_DATA_FMT_ARGB8888  (0U << VOP2_ESMART_REGION0_MST_CTL_DATA_FMT_SHIFT)
#define  VOP2_ESMART_REGION0_MST_CTL_MST_ENABLE         BIT0
#define VOP2_ESMART_REGION0_MST_YRGB(n)         (VOP2_ESMARTn_BASE(n) + 0x0014)
#define VOP2_ESMART_REGION0_MST_CBCR(n)         (VOP2_ESMARTn_BASE(n) + 0x0018)
#define VOP2_ESMART_REGION0_VIR(n)              (VOP2_ESMARTn_BASE(n) + 0x001C)
#define VOP2_ESMART_REGION0_ACT_INFO(n)         (VOP2_ESMARTn_BASE(n) + 0x0020)
#define VOP2_ESMART_REGION0_DSP_INFO(n)         (VOP2_ESMARTn_BASE(n) + 0x0024)
#define VOP2_ESMART_REGION0_DSP_OFFSET(n)       (VOP2_ESMARTn_BASE(n) + 0x0028)
#define VOP2_ESMART_REGION0_SCL_CTRL(n)         (VOP2_ESMARTn_BASE(n) + 0x0030)
#define VOP2_ESMART_REGION0_SCL_FACTOR_YRGB(n)  (VOP2_ESMARTn_BASE(n) + 0x0034)
#define VOP2_ESMART_REGION0_SCL_FACTOR_CBCR(n)  (VOP2_ESMARTn_BASE(n) + 0x0038)
#define VOP2_ESMART_REGION0_SCL_OFFSET(n)       (VOP2_ESMARTn_BASE(n) + 0x003C)
#define VOP2_ESMART_REGION1_MST_CTL(n)          (VOP2_ESMARTn_BASE(n) + 0x0040)
#define VOP2_ESMART_REGION1_MST_YRGB(n)         (VOP2_ESMARTn_BASE(n) + 0x0044)
#define VOP2_ESMART_REGION1_MST_CBCR(n)         (VOP2_ESMARTn_BASE(n) + 0x0048)
#define VOP2_ESMART_REGION1_VIR(n)              (VOP2_ESMARTn_BASE(n) + 0x004C)
#define VOP2_ESMART_REGION1_ACT_INFO(n)         (VOP2_ESMARTn_BASE(n) + 0x0050)
#define VOP2_ESMART_REGION1_DSP_INFO(n)         (VOP2_ESMARTn_BASE(n) + 0x0054)
#define VOP2_ESMART_REGION1_DSP_OFFSET(n)       (VOP2_ESMARTn_BASE(n) + 0x0058)
#define VOP2_ESMART_REGION1_SCL_CTRL(n)         (VOP2_ESMARTn_BASE(n) + 0x0060)
#define VOP2_ESMART_REGION1_SCL_FACTOR_YRGB(n)  (VOP2_ESMARTn_BASE(n) + 0x0064)
#define VOP2_ESMART_REGION1_SCL_FACTOR_CBCR(n)  (VOP2_ESMARTn_BASE(n) + 0x0068)
#define VOP2_ESMART_REGION1_SCL_OFFSET(n)       (VOP2_ESMARTn_BASE(n) + 0x006C)
#define VOP2_ESMART_REGION2_MST_CTL(n)          (VOP2_ESMARTn_BASE(n) + 0x0070)
#define VOP2_ESMART_REGION2_MST_YRGB(n)         (VOP2_ESMARTn_BASE(n) + 0x0074)
#define VOP2_ESMART_REGION2_MST_CBCR(n)         (VOP2_ESMARTn_BASE(n) + 0x0078)
#define VOP2_ESMART_REGION2_VIR(n)              (VOP2_ESMARTn_BASE(n) + 0x007C)
#define VOP2_ESMART_REGION2_ACT_INFO(n)         (VOP2_ESMARTn_BASE(n) + 0x0080)
#define VOP2_ESMART_REGION2_DSP_INFO(n)         (VOP2_ESMARTn_BASE(n) + 0x0084)
#define VOP2_ESMART_REGION2_DSP_OFFSET(n)       (VOP2_ESMARTn_BASE(n) + 0x0088)
#define VOP2_ESMART_REGION2_SCL_CTRL(n)         (VOP2_ESMARTn_BASE(n) + 0x0090)
#define VOP2_ESMART_REGION2_SCL_FACTOR_YRGB(n)  (VOP2_ESMARTn_BASE(n) + 0x0094)
#define VOP2_ESMART_REGION2_SCL_FACTOR_CBCR(n)  (VOP2_ESMARTn_BASE(n) + 0x0098)
#define VOP2_ESMART_REGION2_SCL_OFFSET(n)       (VOP2_ESMARTn_BASE(n) + 0x009C)
#define VOP2_ESMART_REGION3_MST_CTL(n)          (VOP2_ESMARTn_BASE(n) + 0x00A0)
#define VOP2_ESMART_REGION3_MST_YRGB(n)         (VOP2_ESMARTn_BASE(n) + 0x00A4)
#define VOP2_ESMART_REGION3_MST_CBCR(n)         (VOP2_ESMARTn_BASE(n) + 0x00A8)
#define VOP2_ESMART_REGION3_VIR(n)              (VOP2_ESMARTn_BASE(n) + 0x00AC)
#define VOP2_ESMART_REGION3_ACT_INFO(n)         (VOP2_ESMARTn_BASE(n) + 0x00B0)
#define VOP2_ESMART_REGION3_DSP_INFO(n)         (VOP2_ESMARTn_BASE(n) + 0x00B4)
#define VOP2_ESMART_REGION3_DSP_OFFSET(n)       (VOP2_ESMARTn_BASE(n) + 0x00B8)
#define VOP2_ESMART_REGION3_SCL_CTRL(n)         (VOP2_ESMARTn_BASE(n) + 0x00C0)
#define VOP2_ESMART_REGION3_SCL_FACTOR_YRGB(n)  (VOP2_ESMARTn_BASE(n) + 0x00C4)
#define VOP2_ESMART_REGION3_SCL_FACTOR_CBCR(n)  (VOP2_ESMARTn_BASE(n) + 0x00C8)
#define VOP2_ESMART_REGION3_SCL_OFFSET(n)       (VOP2_ESMARTn_BASE(n) + 0x00CC)
#define VOP2_ESMART_KEY_CTRL(n)                 (VOP2_ESMARTn_BASE(n) + 0x00D0)
#define VOP2_ESMART_BG_EN(n)                    (VOP2_ESMARTn_BASE(n) + 0x00D4)

#endif /* RK356XVOP2_H__ */